As a solid-state imaging device, for example, a CMOS image sensor has a configuration in which a sample hold signal conversion circuit disposed for each column in a pixel array acquires a voltage signal outputted by each pixel in a selected row in the pixel array according to an amount of light and converts the voltage signal into a digital signal, and a selected sample hold signal conversion circuit in a column sequentially transfers the converted digital signals to a signal processing circuit and performs image processing on the digital signals, and thereby a predetermined two-dimensional image is obtained.
The sample hold signal conversion circuit includes an analog-digital converter (ADC) that converts a voltage signal outputted by a pixel into, for example, a 10-bit digital signal, a register circuit that holds the 10-bit digital signal, and a data transfer circuit that transfers in parallel the 10-bit digital signal held by the register circuit to the signal processing circuit.
In summary, the sample hold signal conversion circuit in a conventional CMOS image sensor includes data transfer circuits, the number of which is the same as the number of bits of the converted digital signal in the column direction, and each of which is configured to transfer data one bit at a time for each column. However, in recent years, the number of pixels included in a CMOS image sensor tends to increase, and as the number of pixels increases, the number of columns also increases. Therefore, in the conventional transfer method in which data is transferred one bit at a time for each column, there are problems that the circuit scale of the data transfer circuit increases and the data transfer takes a long time.